In the design of a PLL a critical issue is the design of the phase detector as it includes a number of factors that limit performance of the PLL. A conventional analog PLL typically is constructed as shown in FIG. 1. In this Figure a phase detector determines the difference between two phase signals, one being the feedback signal and the other being the reference signal. The output of the phase detector is fed to a filter section, which may for instance be P type only (Proportional) but typically will be PI type (Proportional-Integral), providing a so-called type II PLL. The filter feeds to a controlled oscillator, which in FIG. 1 is a voltage or current controlled oscillator. The frequency generated by the controlled oscillator is divided and fed back to the input of the phase
The analysis of such a Phase Locked Loop or PLL is typically done using Black's formula to analyze bandwidth of the closed loop, overshoot, peaking and the like.
Analog PLL's have several limitations for which digital PLLs have a much better performance. This results from the different nature of digital PLL. In a digital PLL the phase signal is sampled and used to control a digitally controlled oscillator or DCO. Digital PLLs have several advantages including simple and accurate holdover. If there is no reference signal available a digital PLL can use its current or an historic DCO setting to maintain the same output frequency without any error in the digital control value. A digital PLL will typically rely on stability of its clock signal to achieve this, which mostly will come from a crystal oscillator. Analog PLLs will have other, less stable elements in their structure to rely upon.
A digital PLL will have no difficulty providing extreme bandwidths in the order of 10 MHz, which is very difficult for analog PLLs. A digital PLL relies on the stability of its clock.
A digital PLL can handle extremely low input frequencies such as 1 Hz. An analog PLL will introduce a lot of noise of the phase detector, charge pump and the like, as all noise of the analog elements will be folded back into a small frequency band. The noise of the crystal of a digital PLL will also be folded back, but remain much lower in absolute size. A typical digital PLL looks a lot like an analog PLL and is shown in FIG. 2. A sampling unit supplies the input to the phase detector which in turn supplies the signal to the digital filter, the DCO and frequency synthesizer. However, digital PLLs are susceptible to the additional of noise that is added to the feedback signal during the re-sampling process.
Examples of typical prior art circuits are shown in U.S. Pat. Nos. 5,602,884; 7,006,590; and 5,905,388.